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PE64905
Product Specification
Serial Interface Operation and Sharing
The Bus Master initiates the start of serial
transaction by driving SDA (Serial Data) low while
CLK (Serial Clock) remains high. Each bit of the
18-bit telegram is clocked in on the rising edge of
SCL. Transitions on SDA are allowed only when
SCL is low. The DTC activates the data on the
rising edge of the clock pulse for the
acknowledgement bit following the data word.
Please refer to Peregrine Application note AN28 for
more information regarding the interface.
The DTC can be configured for two different
addresses via ADDR pin. Tying ADDR pin to V DD
sets the address to 113. Tying ADDR to GND sets
the address to 112. Data (SDA), Clock (SCL), and
V DD lines may be shared between each DTC.
Figure 16. Serial Interface Timing Diagram (oscilloscope view)
Table 5. Register Map
Figure 17. Recommended Bus Sharing
b7
0
b6
0
b5
STB*
b4
d4
b3
d3
b2
d2
b1
d1
b0
d0
MSB
(first in)
Note 1: The DTC is active when low (set to 0) and in
low-current stand-by mode when high (set to 1)
LSB
(last in)
Table 6. Serial Interface Timing Characteristics
V DD = 2.6V, -40°C < T A < 85°C, unless otherwise specified
Symbol
f CLK
t R
t F
Parameter
Serial Clock Frequency
SCL, SDA Rise Time
SCL, SDA Fall Time
Min
Max
400
100
100
Units
kHz
nS
nS
Table 7. Address Mapping
ADDR
State
GND
V DD
Address
(DEC)
112
113
Address
(HEX)
0x70
0x71
Address (BIN)
1110000
1110001
Document No. 70-0335-06 │ www.psemi.com
?2011-2012 Peregrine Semiconductor Corp. All rights reserved.
Page 7 of 11
Logo updated under non-rev change. Peregrine products are protected under one or more of the following U.S. Patents: http://patents.psemi.com
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